1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to render pipelines.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the interconnect systems tasked with moving data between graphics sub-systems. In addition to the volume of graphics data and the speed with which it must be handled, there are often problems encountered associated with the synchronicity of data. Frequently it is found that individual components of the graphics stream have varying processing times associated with them, making the use of a synchronous stream difficult or inefficient.
In order to move large amounts of high-speed data from one sub-system to another, wide, high-speed buses are often constructed. One example of such a bus may be represented by UPA (Ultra Port Architecture). Due to the non-continuous nature of some types of graphics data, the bus may not be fully utilized. The unused bus capacity may be observed as empty or invalid data words embedded in the stream. These empty data words may adversely affect the optimal performance of down-stream elements in the render pipe-line if these elements are designed to operate synchronously, and if they are dependent on multiple word data.
The use of FIFO type memories is effective in regulating streams where the data rate may be variable. However, the use of a FIFO may be problematic where the interfacing bus is wide, and contains sporadically placed empty data words. Therefore, for these reasons, a system and method for improving the packing of data in a graphics queue, is highly desired. A system and method is also desired for improved retrieval of data from a graphics queue, wherein ordering of the graphics data is maintained during retrieval of the graphics data.